The present invention relates to a semiconductor integrated circuit design supporting method, a semiconductor integrated circuit design supporting system, and a computer readable medium.
A semiconductor integrated circuit device includes a semiconductor chip (die) on which logic circuits are mounted, and a semiconductor package covering the semiconductor chip. Widely used semiconductor packages include those which enable high-density packaging, such as a BGA (ball grid array) package or a PGA (pin grid array) package, for a circuit board to be incorporated into electronic equipment.
In LSI devices, when a plurality of output terminals are simultaneously involved in an operation change from a low level to a high level or vice versa, charge/discharge current of output load capacity instantly flows through a power supply and a ground line. Depending on the magnitude of the current, noise, which is so-called “simultaneous switching noise”, may be caused in the power supply and the grounding line.
To take measure for the simultaneous switching noise, the number of pads required for the entire chip has been estimated by multiplying a drive factor of an IO cell with an inductance coefficient of a package, summing up the obtained products, and dividing the sum by a noise tolerance for one power supply pin.
However, neither a method has been established yet for properly laying out such power supply pads after the estimation of a required number of pads, nor a tool has been provided for examining the risk of the simultaneous switching noise. Under such circumstances, analysis for signals/power supply is obliged to be carried out after completing chip layout and package designing. In this case, if a problem of the simultaneous switching is found out, the layout of the power supply pads has to be changed to again carry out chip layout and package designing. Thus, it has been a problem that the time required for designing is prolonged.